 |
CPU Detection
Submitted by |
This is a basic CPU detection class I have written as part of my project
called DXWrapper. It detects the CPU's name and its capabilites and it
recodnizes Intel and AMD processors.
The class is based on the CPUID instruction so it doesnt support older CPUs
who didnt have this direction.
You can check my project's page at http://www.geocities.com/dxwrapper.
I've included the class itself (DXWCPU.h and DXWCPU.cpp) and a sample
application.
|
Currently browsing [cpuid.zip] (27,328 bytes) - [DXWCPU.cpp] - (8,858 bytes)
#include <windows.h>
#include <stdlib.h>
#include <stdio.h>
#include "DXWCPU.h"
#define MHZ_MILLIS (500) // 0.005 accurate
DXWCPU::DXWCPU(void)
{
m_CPUGotInfo = false;
m_CPU_Features = 0;
m_CPU_MHZ = 0;
m_CPU_PerformanceFreq = 1.0f;
m_CPU_SecondsPerClock = 1.0f;
m_MaxCPUIDVal = 0;
m_ProcType = 0;
m_ProcFamily = 0;
m_ProcModel = 0;
m_ProcStepping = 0;
uint32 m_L2Cache = 0;
GetInfo();
}
//--------------------------------------------------------------------------------------------------------------------------------
// CPUID routins
//--------------------------------------------------------------------------------------------------------------------------------
// Execute CPUID function EAX=funcNum and get EAX result
uint32 DXWCPU::GetCPUID_EAX(uint32 funcNum)
{
uint32 retval;
__try
{
_asm
{
mov eax, funcNum
CPUID
mov retval, eax
}
}
__except(EXCEPTION_EXECUTE_HANDLER)
{
retval = 0;
}
return retval;
}
// Execute CPUID function EAX=funcNum and get EDX result
uint32 DXWCPU::GetCPUID_EDX(uint32 funcNum)
{
uint32 retval;
__try
{
_asm
{
mov eax, funcNum
CPUID
mov retval, edx
}
}
__except(EXCEPTION_EXECUTE_HANDLER)
{
retval = 0;
}
return retval;
}
// Execute CPUID EAX=funcNum and get EAX result and
// the string EBX:EDX:ECX
uint32 DXWCPU::GetCPUIDString(uint32 funcNum, char *String)
{
uint32 retval;
__try
{
_asm
{
mov eax,funcNum
CPUID
mov retval,eax
mov eax,String
mov dword ptr[eax],ebx
mov dword ptr[eax+4],edx
mov dword ptr[eax+8],ecx
}
}__except(EXCEPTION_EXECUTE_HANDLER)
{
retval =0;
}
return retval;
}
// AMD Specific:
// In the AMD processor extended EAX functions 8000_0002h, 8000_0003h,
// and 8000_0004h return an ASCII string containing the name of the processor.
void DXWCPU::GetCPUIDStringAMD(uint32 funcNum, char *String)
{
uint32 retval;
__try
{
_asm
{
mov eax,funcNum
CPUID
mov retval,eax
mov eax,String
mov dword ptr[eax+4],ebx
mov dword ptr[eax+8],ecx
mov ebx,retval
mov dword ptr[eax+12],edx
mov dword ptr[eax],ebx
}
}
__except(EXCEPTION_EXECUTE_HANDLER)
{
retval =0;
}
}
int64 DXWCPU::GetRDTSC(void)
{
int64 clock;
_asm
{
push ebx
push ecx
xor eax,eax
CPUID
RDTSC
mov dword ptr clock,eax
mov dword ptr clock+4,edx
xor eax,eax
CPUID
pop ecx
pop ebx
}
return clock;
}
uint32 DXWCPU::GetRDTSCOverHead(void)
{
uint32 Elap, MinOverhead =0xffffff;
int64 start;
int x;
for(x=0;x < 50;x++)
{
start =GetRDTSC();
Elap =(uint32)(GetRDTSC() - start);
MinOverhead =min(MinOverhead, Elap);
}
return MinOverhead;
}
//--------------------------------------------------------------------------------------------------------------------------------
// MHZ measuring routins
//--------------------------------------------------------------------------------------------------------------------------------
static int64 StartClock;
static uint32 StartTime;
uint32 RoundMHZ(uint32 MHZ)
{
const uint32 NF[9] = {0, 20, 33, 50, 60, 66, 80, 90, 100};
uint32 Freq, RF;
uint8 i;
uint8 Hi, Lo;
RF = 0;
Freq = MHZ % 100;
for (i = 0; i<8; i++)
{
if (Freq < NF[i])
{
Hi = i;
Lo = i - 1;
if ((NF[Hi] - Freq) > (Freq - NF[Lo]))
RF = NF[Lo] - Freq;
else
RF = NF[Hi] - Freq;
break;
}
}
return MHZ + RF;
}
void DXWCPU::StartGetMHZ(void)
{
StartClock = GetRDTSC();
StartTime = timeGetTime();
}
uint32 DXWCPU::GetMHZ(void)
{
int64 ElapsedClock;
uint32 ElapsedTime, MHZ;
do
{
ElapsedTime = timeGetTime() - StartTime;
}
while (ElapsedTime < MHZ_MILLIS);
ElapsedClock = GetRDTSC() - StartClock;
MHZ = (uint32)(ElapsedClock/(1000*ElapsedTime));
// Check for errors
// uint32 Z50,Z83;
/* Z50 = ((MHZ + 25)/50)*50; // round to the nearest fifty
Z83 = (int)((MHZ + 41)*12/1000)*1000/12; // round to the nearest 83.333 == 1000/12*/
MHZ=RoundMHZ(MHZ);
return MHZ;
}
bool DXWCPU::GetPerformanceFreq(void)
{
LARGE_INTEGER Freq;
if (!QueryPerformanceFrequency(&Freq))
{
return false;
}
m_CPU_PerformanceFreq = (float)Freq.LowPart;
return true;
}
//--------------------------------------------------------------------------------------------------------------------------------
bool DXWCPU::GetInfo(void)
{
uint32 TypeFlags = 0;
if (m_CPUGotInfo)
return true;
m_CPUGotInfo = true;
StartGetMHZ();
// Get the CPU vendor string using the standard EAX=0
// function. the CPUID instruction will return a 12chars
// vendor string
ZeroMemory(m_ProcVendorString,sizeof(m_ProcVendorString));
m_MaxCPUIDVal = GetCPUIDString(0, m_ProcVendorString);
if ((strncmp(m_ProcVendorString, VENDOR_INTEL, 12))==0)
{
// CPU vendor is Intel
// Get features flag
TypeFlags = GetCPUID_EDX(0x1);
m_CPU_Features = TypeFlags;
TypeFlags = GetCPUID_EAX(1);
m_ProcType = (TypeFlags>>12) & 0x3;
m_ProcFamily = (TypeFlags>>8) & 0xf;
m_ProcModel = (TypeFlags>>4) & 0xf;
m_ProcStepping = (TypeFlags) & 0x7;
sprintf(m_ProcName,GetIntelProcName(m_ProcType, m_ProcFamily, m_ProcModel, m_ProcStepping));
}
else if ((strncmp(m_ProcVendorString, VENDOR_AMD, 12))==0)
{
TypeFlags = GetCPUID_EAX(0x80000000);
if (TypeFlags) // Extended functions supported
{
TypeFlags = GetCPUID_EDX(0x80000001);
m_CPU_Features = TypeFlags;
GetCPUIDStringAMD(0x80000002, m_ProcName);
GetCPUIDStringAMD(0x80000003, m_ProcName+16);
GetCPUIDStringAMD(0x80000004, m_ProcName+32);
}
else
{
TypeFlags = GetCPUID_EDX(0x1);
m_CPU_Features = TypeFlags;
}
TypeFlags = GetCPUID_EAX(1);
m_ProcType =(TypeFlags>>12) & 0x3;
m_ProcFamily =(TypeFlags>>8) & 0xf;
m_ProcModel =(TypeFlags>>4) & 0xf;
m_ProcStepping =(TypeFlags) & 0x7;
}
GetPerformanceFreq();
m_CPU_MHZ = GetMHZ();
m_CPU_SecondsPerClock = 1.0f / ( 1000000.0f * m_CPU_MHZ );
return true;
}
char* DXWCPU::GetIntelProcName(uint32 Type, uint32 Family, uint32 Model, uint32 Stepping)
{
char *CPUName = NULL;
switch (Family)
{
case 4: if (Model == 4) CPUName = INTEL_486SL;
if (Model == 7) CPUName = INTEL_DX2WB;
if (Model == 8) CPUName = INTEL_DX4;
if ((Model == 8)&&(Type==1)) CPUName = INTEL_DX4O;
break;
case 5: if (Model == 1) CPUName = INTEL_P;
if (Model == 2) CPUName = INTEL_P;
if ((Model == 1)&&(Type==1)) CPUName = INTEL_PO;
if ((Model == 2)&&(Type==1)) CPUName = INTEL_PO;
if ((Model == 3)&&(Type==1)) CPUName = INTEL_PO;
if (Model == 3) CPUName = INTEL_P;
if (Model == 4) CPUName = INTEL_P;
if ((Model == 4)&&(Type==1)) CPUName = INTEL_PO;
break;
case 6: if (Model == 1) CPUName = INTEL_PPRO;
if (Model == 3) CPUName = INTEL_PII;
if ((Model == 3)&&(Type=1)) CPUName = INTEL_PIIO;
if (Model == 5) CPUName = INTEL_PII;
if (Model == 6) CPUName = INTEL_CELERON;
if (Model == 7) CPUName = INTEL_PIII;
if (Model == 8) CPUName = INTEL_PIII;
if (Model == 10) CPUName = INTEL_XEON;
break;
default: CPUName = PROCESSOR_UNKNOWN; break;
}
return CPUName;
}
void DXWCPU::GetIntelCacheDescription(uint8 D, char* Desc)
{
switch (D)
{
case 0x01 : sprintf(Desc,"Instruction TLB, 4Kb pages, 4-way set associative, 32 entries"); break;
case 0x02 : sprintf(Desc,"Instruction TLB, 4Mb pages, fully associative, 2 entries"); break;
case 0x03 : sprintf(Desc,"Data TLB, 4Kb pages, 4-way set associative, 64 entries"); break;
case 0x04 : sprintf(Desc,"Data TLB, 4Mb pages, 4-way set associative, 8 entries"); break;
case 0x06 : sprintf(Desc,"8KB instruction cache, 4-way set associative, 32 byte line size"); break;
case 0x08 : sprintf(Desc,"16KB instruction cache, 4-way set associative, 32 byte line size"); break;
case 0x0A : sprintf(Desc,"8KB data cache 2-way set associative, 32 byte line size"); break;
case 0x0C : sprintf(Desc,"16KB data cache, 4-way set associative, 32 byte line size"); break;
case 0x40 : sprintf(Desc,"No L2 cache"); break;
case 0x41 : sprintf(Desc,"Unified cache, 32 byte cache line, 4-way set associative, 128Kb"); break;
case 0x42 : sprintf(Desc,"Unified cache, 32 byte cache line, 4-way set associative, 256Kb"); break;
case 0x43 : sprintf(Desc,"Unified cache, 32 byte cache line, 4-way set associative, 512Kb"); break;
case 0x44 : sprintf(Desc,"Unified cache, 32 byte cache line, 4-way set associative, 1Mb"); break;
case 0x45 : sprintf(Desc,"Unified cache, 32 byte cache line, 4-way set associative, 2Mb"); break;
}
}
|
|
Currently browsing [cpuid.zip] (27,328 bytes) - [DXWCPU.h] - (12,297 bytes)
#ifndef DXWCPU_H
#define DXWCPU_H
typedef __int64 int64;
typedef __int32 int32;
typedef __int16 int16;
typedef __int8 int8;
typedef unsigned __int64 uint64;
typedef unsigned __int32 uint32;
typedef unsigned __int16 uint16;
typedef unsigned __int8 uint8;
#define VENDOR_INTEL "GenuineIntel"
#define VENDOR_AMD "AuthenticAMD"
// Standard (Intel) Feature Flags
#define INTEL_FPU_FLAG 0x00000001 // Bit 0 - Floating-Point unit on chip
#define INTEL_VME_FLAG 0x00000002 // Bit 1 - Virtual Mode Extention
#define INTEL_DE_FLAG 0x00000004 // Bit 2 - Debugging Extention
#define INTEL_PSE_FLAG 0x00000008 // Bit 3 - Page Size Extention
#define INTEL_TSC_FLAG 0x00000010 // Bit 4 - Time Stamp Counter
#define INTEL_MSR_FLAG 0x00000020 // Bit 5 - Model Specific Registers
#define INTEL_PAE_FLAG 0x00000040 // Bit 6 - Physical Address Extention
#define INTEL_MCE_FLAG 0x00000080 // Bit 7 - Machine Check Exception
#define INTEL_CX8_FLAG 0x00000100 // Bit 8 - CMPXCHG8 Instruction
#define INTEL_APIC_FLAG 0x00000200 // Bit 9 - Software-accessible local APIC on Chip
#define INTEL_BIT_10 0x00000400 // Bit 10 - Reserved, do not count on value
#define INTEL_SEP_FLAG 0x00000800 // Bit 11 - Fast System Call
#define INTEL_MTRR_FLAG 0x00001000 // Bit 12 - Memory Type Range Registers
#define INTEL_PGE_FLAG 0x00002000 // Bit 13 - Page Global Enable
#define INTEL_MCA_FLAG 0x00004000 // Bit 14 - Machine Check Architecture
#define INTEL_CMOV_FLAG 0x00008000 // Bit 15 - Conditional Move Instruction
#define INTEL_PAT_FLAG 0x00010000 // Bit 16 - Page Attribute Table
#define INTEL_PSE36_FLAG 0x00020000 // Bit 17 - 36-bit Page Size Extention
#define INTEL_PN_FLAG 0x00040000 // Bit 18 - Processor Number
#define INTEL_BIT_19 0x00080000 // Bit 19 - Reserved, do not count on value
#define INTEL_BIT_20 0x00100000 // Bit 20 - Reserved, do not count on value
#define INTEL_BIT_21 0x00200000 // Bit 21 - Reserved, do not count on value
#define INTEL_BIT_22 0x00400000 // Bit 22 - Reserved, do not count on value
#define INTEL_MMX_FLAG 0x00800000 // Bit 23 - MMX technology
#define INTEL_FXSR_FLAG 0x01000000 // Bit 24 - Fast Floating Point Save and Restore
#define INTEL_SSE_FLAG 0x02000000 // Bit 25 - Streaming SIMD Extension
#define INTEL_SSE2_FLAG 0x04000000 // Bit 26 - SSE2
#define INTEL_BIT_27 0x08000000 // Bit 27 - Reserved, do not count on value
#define INTEL_BIT_28 0x10000000 // Bit 28 - Reserved, do not count on value
#define INTEL_BIT_29 0x20000000 // Bit 29 - Reserved, do not count on value
#define INTEL_64BIT_FLAG 0x40000000 // Bit 30 - 64bit Intel Architecture
#define INTEL_BIT_31 0x80000000 // Bit 31 - Reserved, do not count on value
// AMD Standard Feature Flags
#define AMD_FPU_FLAG 0x00000001 // Bit 0 - Floating-Point unit on chip
#define AMD_VME_FLAG 0x00000002 // Bit 1 - Virtual Mode Extention
#define AMD_DE_FLAG 0x00000004 // Bit 2 - Debugging Extention
#define AMD_PSE_FLAG 0x00000008 // Bit 3 - Page Size Extention
#define AMD_TSC_FLAG 0x00000010 // Bit 4 - Time Stamp Counter
#define AMD_MSR_FLAG 0x00000020 // Bit 5 - Model Specific Registers
#define AMD_PEA_FLAG 0x00000040 // Bit 6 - Page Address Extension
#define AMD_MCE_FLAG 0x00000080 // Bit 7 - Machine Check Exception
#define AMD_CX8_FLAG 0x00000100 // Bit 8 - CMPXCHG8 Instruction
#define AMD_APIC_FLAG 0x00000200 // Bit 9 - On-chip APIC
#define AMD_BIT_10 0x00000400 // Bit 10 - Reserved, do not count on value
#define AMD_BIT_11 0x00000800 // Bit 11 - Reserved, do not count on value
#define AMD_MTRR_FLAG 0x00001000 // Bit 12 - Memory Type Range Registers
#define AMD_PGE_FLAG 0x00002000 // Bit 13 - Page Global Enable
#define AMD_MCA_FLAG 0x00004000 // Bit 14 - Machine Check Architecture
#define AMD_ICMOV_FLAG 0x00008000 // Bit 15 - Integer Conditional Move Instruction
#define AMD_PAT_FLAG 0x00010000 // Bit 16 - Page Attribute Table
#define AMD_PSE36_17 0x00020000 // Bit 17 - 36-bit Page Size Extension
#define AMD_BIT_18 0x00040000 // Bit 18 - Reserved, do not count on value
#define AMD_BIT_19 0x00080000 // Bit 19 - Reserved, do not count on value
#define AMD_BIT_20 0x00100000 // Bit 20 - Reserved, do not count on value
#define AMD_BIT_21 0x00200000 // Bit 21 - Reserved, do not count on value
#define AMD_BIT_22 0x00400000 // Bit 22 - Reserved, do not count on value
#define AMD_MMX_FLAG 0x00800000 // Bit 23 - MMX technology
#define AMD_FXSR_FLAG 0x01000000 // Bit 24 - Fast floating point save and restore
#define AMD_BIT_25 0x02000000 // Bit 25 - Reserved, do not count on value
#define AMD_BIT_26 0x04000000 // Bit 26 - Reserved, do not count on value
#define AMD_BIT_27 0x08000000 // Bit 27 - Reserved, do not count on value
#define AMD_BIT_28 0x10000000 // Bit 28 - Reserved, do not count on value
#define AMD_BIT_29 0x20000000 // Bit 29 - Reserved, do not count on value
#define AMD_BIT_30 0x40000000 // Bit 30 - Reserved, do not count on value
#define AMD_BIT_31 0x80000000 // Bit 31 - Reserved, do not count on value
// Bit#define AMD Enhanced Feature Flags
#define EAMD_FPU_FLAG 0x00000001 // Bit 0 - Floating-Point unit on chip
#define EAMD_VME_FLAG 0x00000002 // Bit 1 - Virtual Mode Extention
#define EAMD_DE_FLAG 0x00000004 // Bit 2 - Debugging Extention
#define EAMD_PSE_FLAG 0x00000008 // Bit 3 - Page Size Extention
#define EAMD_TSC_FLAG 0x00000010 // Bit 4 - Time Stamp Counter
#define EAMD_MSR_FLAG 0x00000020 // Bit 5 - Model Specific Registers
#define EAMD_PEA_FLAG 0x00000040 // Bit 6 - Page Address Extension
#define EAMD_MCE_FLAG 0x00000080 // Bit 7 - Machine Check Exception
#define EAMD_CX8_FLAG 0x00000100 // Bit 8 - CMPXCHG8 Instruction
#define EAMD_APIC_FLAG 0x00000200 // Bit 9 - On-chip APIC
#define EAMD_BIT_10 0x00000400 // Bit 10 - Reserved, do not count on value
#define EAMD_SEP_FLAG 0x00000800 // Bit 11 - Fast System Call
#define EAMD_MTRR_FLAG 0x00001000 // Bit 12 - Memory Type Range Registers
#define EAMD_PGE_FLAG 0x00002000 // Bit 13 - Page Global Enable
#define EAMD_MCA_FLAG 0x00004000 // Bit 14 - Machine Check Architecture
#define EAMD_ICMOV_FLAG 0x00008000 // Bit 15 - Integer Conditional Move Instruction
#define EAMD_PAT_FLAG 0x00010000 // Bit 16 - Page Attribute Table
#define EAMD_PSE36_17 0x00020000 // Bit 17 - 36-bit Page Size Extension
#define EAMD_BIT_18 0x00040000 // Bit 18 - Reserved, do not count on value
#define EAMD_BIT_19 0x00080000 // Bit 19 - Reserved, do not count on value
#define EAMD_BIT_20 0x00100000 // Bit 20 - Reserved, do not count on value
#define EAMD_BIT_21 0x00200000 // Bit 21 - Reserved, do not count on value
#define EAMD_AMIE_FLAG 0x00400000 // Bit 22 - AMD Multimedia Instructions Extensions
#define EAMD_MMX_FLAG 0x00800000 // Bit 23 - MMX technology
#define EAMD_FXSR_FLAG 0x01000000 // Bit 24 - Fast floating point save and restore
#define EAMD_BIT_25 0x02000000 // Bit 25 - Reserved, do not count on value
#define EAMD_BIT_26 0x04000000 // Bit 26 - Reserved, do not count on value
#define EAMD_BIT_27 0x08000000 // Bit 27 - Reserved, do not count on value
#define EAMD_BIT_28 0x10000000 // Bit 28 - Reserved, do not count on value
#define EAMD_BIT_29 0x20000000 // Bit 29 - Reserved, do not count on value
#define EAMD_3DNOWEXT_FLAG 0x40000000 // Bit 30 - AMD 3DNOW! Extensions
#define EAMD_3DNOW_FLAG 0x80000000 // Bit 31 - AMD 3DNOW! Technology
// Intel processor names
#define INTEL_486SL "486(TM) SL processor"
#define INTEL_DX2WB "Write-Back Enhanced DX2(TM) processor"
#define INTEL_DX4 "DX4(TM) processor"
#define INTEL_DX4O "DX4(TM) OverDrive(R) processor"
#define INTEL_P "Pentium(R) processor"
#define INTEL_PO "Pentium(R) OverDrive(R) processor"
#define INTEL_PPRO "Pentium(R) Pro processor"
#define INTEL_PII "Pentium(R) II processor"
#define INTEL_CELERON "Celeron(TM) processor"
#define INTEL_PIII "Pentium(R) III processor"
#define INTEL_XEON "Pentium(R) III Xeon processor"
#define INTEL_PIIO "Pentium(R) II OverDrive(R) processor"
#define PROCESSOR_UNKNOWN "Unknown processor"
class DXWCPU
{
public:
// Constructor/Destructor
DXWCPU(void);
bool GetInfo(void);
// Accessors
/* Standard CPU Features */
bool CPU_Has_FPU() { return ((m_CPU_Features & INTEL_FPU_FLAG) ==INTEL_FPU_FLAG); }
bool CPU_Has_VME() { return ((m_CPU_Features & INTEL_VME_FLAG) ==INTEL_VME_FLAG); }
bool CPU_Has_DE() { return ((m_CPU_Features & INTEL_DE_FLAG) ==INTEL_DE_FLAG); }
bool CPU_Has_PSE() { return ((m_CPU_Features & INTEL_PSE_FLAG) ==INTEL_PSE_FLAG); }
bool CPU_Has_TSC() { return ((m_CPU_Features & INTEL_TSC_FLAG) ==INTEL_TSC_FLAG); }
bool CPU_Has_MSR() { return ((m_CPU_Features & INTEL_MSR_FLAG) ==INTEL_MSR_FLAG); }
bool CPU_Has_PAE() { return ((m_CPU_Features & INTEL_PAE_FLAG) ==INTEL_PAE_FLAG); }
bool CPU_Has_MCE() { return ((m_CPU_Features & INTEL_MCE_FLAG) ==INTEL_MCE_FLAG); }
bool CPU_Has_CX8() { return ((m_CPU_Features & INTEL_CX8_FLAG) ==INTEL_CX8_FLAG); }
bool CPU_Has_SEP() { return ((m_CPU_Features & INTEL_CX8_FLAG) ==INTEL_SEP_FLAG); }
bool CPU_Has_APIC() { return ((m_CPU_Features & INTEL_APIC_FLAG)==INTEL_APIC_FLAG);}
bool CPU_Has_MTRR() { return ((m_CPU_Features & INTEL_MTRR_FLAG)==INTEL_MTRR_FLAG);}
bool CPU_Has_PGE() { return ((m_CPU_Features & INTEL_PGE_FLAG) ==INTEL_PGE_FLAG); }
bool CPU_Has_MCA() { return ((m_CPU_Features & INTEL_MCA_FLAG) ==INTEL_MCA_FLAG); }
bool CPU_Has_CMOV() { return ((m_CPU_Features & INTEL_CMOV_FLAG)==INTEL_CMOV_FLAG);}
bool CPU_Has_PAT() { return ((m_CPU_Features & INTEL_PAT_FLAG) ==INTEL_PAT_FLAG); }
bool CPU_Has_PSE36(){ return ((m_CPU_Features & INTEL_PSE36_FLAG)==INTEL_PSE36_FLAG);}
bool CPU_Has_MMX() { return ((m_CPU_Features & INTEL_MMX_FLAG)==INTEL_MMX_FLAG); }
bool CPU_Has_FXSR() { return ((m_CPU_Features & INTEL_FXSR_FLAG)==INTEL_FXSR_FLAG);}
bool CPU_Has_SSE() { return ((m_CPU_Features & INTEL_SSE_FLAG)==INTEL_SSE_FLAG);}
bool CPU_Has_SSE2() { return ((m_CPU_Features & INTEL_SSE2_FLAG)==INTEL_SSE2_FLAG);}
bool CPU_Has_64BIT() { return ((m_CPU_Features & INTEL_64BIT_FLAG)==INTEL_64BIT_FLAG);}
// AMD Specific
bool CPU_Has_AMD3DNOW() { return ((m_CPU_Features & EAMD_3DNOW_FLAG)==EAMD_3DNOW_FLAG); }
bool CPU_Has_AMD3DNOWEXT() { return ((m_CPU_Features & EAMD_3DNOWEXT_FLAG)==EAMD_3DNOWEXT_FLAG);}
bool CPU_Has_AMIE() { return ((m_CPU_Features & EAMD_3DNOWEXT_FLAG)==EAMD_3DNOWEXT_FLAG); }
char* GetVendorString() { return m_ProcVendorString; }
char* GetCPUName() { return m_ProcName; }
uint32 GetCPUFeatures() { return m_CPU_Features; }
uint32 GetCPUMHZ() { return m_CPU_MHZ; }
float GetPerformance() { return m_CPU_PerformanceFreq; }
float GetSecondsPerClock() { return m_CPU_SecondsPerClock; }
uint32 GetType() { return m_ProcType; }
uint32 GetFamily() { return m_ProcFamily; }
uint32 GetModel() { return m_ProcModel; }
uint32 GetStepping(){ return m_ProcStepping;}
//Functions
char* GetIntelProcName(uint32 Type, uint32 Family, uint32 Model, uint32 Stepping);
void GetIntelCacheDescription(uint8 D, char* Desc);
private:
// Functions
uint32 GetCPUID_EAX(uint32 funcNum);
uint32 GetCPUID_EDX(uint32 funcNum);
uint32 GetCPUIDString(uint32 funcNum, char *String);
void GetCPUIDStringAMD(uint32 funcNum, char *String);
int64 GetRDTSC(void);
uint32 GetRDTSCOverHead(void);
void StartGetMHZ(void);
uint32 GetMHZ(void);
bool GetPerformanceFreq(void);
// Data
bool m_CPUGotInfo;
uint32 m_CPU_Features;
uint32 m_CPU_MHZ;
float m_CPU_PerformanceFreq;
float m_CPU_SecondsPerClock;
uint32 m_MaxCPUIDVal; // Highest value recodnized by CPUID
char m_ProcVendorString[13]; // Vendor name
char m_ProcName[48]; // Processor Name
uint32 m_ProcType; // Processor Type
uint32 m_ProcFamily; // Processor Family
uint32 m_ProcModel; // Processor Model
uint32 m_ProcStepping; // Processor Stepping
};
#endif |
|
Currently browsing [cpuid.zip] (27,328 bytes) - [main.cpp] - (2,665 bytes)
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "DXWCPU.h"
void main()
{
DXWCPU cpu;
printf("\nCPU INFORMATION:\n");
printf("\nCPU Vendor: %s",cpu.GetVendorString() );
printf("\nCPU Name : %s",cpu.GetCPUName() );
printf("\nCPUType: %i \nCPU Family: %i \nCPU Model: %i \nCPU Stepping: %i",
cpu.GetType(),cpu.GetFamily(),cpu.GetModel(),cpu.GetStepping());
printf("\nCPU Speed: %i Mhz \n Performance Frequency: %f \n Seconds per clock: %f \n",
cpu.GetCPUMHZ(), cpu.GetPerformance(), cpu.GetSecondsPerClock());
printf ("\nfeatures = %08x\n", cpu.GetCPUFeatures());
printf ("CPU has FPU: %c\n",
cpu.CPU_Has_FPU() ? 'y' : 'n');
printf ("CPU supports Virtual Mode Extension: %c\n",
cpu.CPU_Has_VME() ? 'y' : 'n');
printf ("CPU supports Debug extension: %c\n",
cpu.CPU_Has_DE() ? 'y' : 'n');
printf ("CPU supports PSE : %c\n",
cpu.CPU_Has_PSE() ? 'y' : 'n');
printf ("CPU supports MSR : %c\n",
cpu.CPU_Has_MSR() ? 'y' : 'n');
printf ("CPU supports PAE %c\n",
cpu.CPU_Has_PAE ? 'y' : 'n');
printf ("CPU supports MCE : %c\n",
cpu.CPU_Has_MCE() ? 'y' : 'n');
printf ("CPU supports CX8 : %c\n",
cpu.CPU_Has_CX8() ? 'y' : 'n');
printf ("CPU supports APIC : %c\n",
cpu.CPU_Has_APIC() ? 'y' : 'n');
printf ("CPU supports SEP : %c\n",
cpu.CPU_Has_SEP() ? 'y' : 'n');
printf ("CPU supports MTRR : %c\n",
cpu.CPU_Has_MTRR() ? 'y' : 'n');
printf ("CPU supports PGE : %c\n",
cpu.CPU_Has_PGE() ? 'y' : 'n');
printf ("CPU supports MCA : %c\n",
cpu.CPU_Has_MCA() ? 'y' : 'n');
printf ("CPU supports CMOV : %c\n",
cpu.CPU_Has_CMOV() ? 'y' : 'n');
printf ("CPU supports PAT : %c\n",
cpu.CPU_Has_PAT() ? 'y' : 'n');
printf ("CPU supports PSE36 : %c\n",
cpu.CPU_Has_PSE36() ? 'y' : 'n');
printf ("CPU supports MMX : %c\n",
cpu.CPU_Has_MMX() ? 'y' : 'n');
printf ("CPU supports FXSR : %c\n",
cpu.CPU_Has_FXSR() ? 'y' : 'n');
printf ("CPU supports SSE : %c\n",
cpu.CPU_Has_SSE() ? 'y' : 'n');
printf ("CPU supports SSE2 : %c\n",
cpu.CPU_Has_SSE2() ? 'y' : 'n');
printf ("CPU supports 64BIT Architecture : %c\n",
cpu.CPU_Has_64BIT() ? 'y' : 'n');
printf ("CPU supports AMD : %c\n",
cpu.CPU_Has_AMD3DNOW() ? 'y' : 'n');
printf ("CPU supports AMD Extension: %c\n",
cpu.CPU_Has_AMD3DNOWEXT() ? 'y' : 'n');
printf ("CPU supports AMD Multimedia Extension : %c\n",
cpu.CPU_Has_AMIE() ? 'y' : 'n');
}
|
|
The zip file viewer built into the Developer Toolbox made use
of the zlib library, as well as the zlibdll source additions.
|
